The present invention relates to integrated packaging, packaged integrated circuits and methods of producing packaged integrated circuits.
Various types of packaged integrated circuits are known in the prior art. The following patents and published patent applications of the present inventor and the references cited therein are believed to represent the state of the art:
U.S. Pat. Nos. 4,551,629; 4,764,846; 4,794,092; 4,862,249; 4,984,358; 5,104,820; 5,126,286; 5,266,833; 5,546,654; 5,567,657; 5,612,570; 5,657,206; 5,661,087; 5,675,180; 5,703,400; 5,837,566; 5,849,623; 5,857,858; 5,859,475; 5,869,353; 5,888,884; 5,891,761; 5,900,674; 5,938,45; 5,985,695; 6,002,163; 6,046,410; 6,080,596; 6,092,280; 6,098,278; 6,124,637; 6,134,118.
EP 490739 A1; JP 63-166710
WO 85/02283; WO 89/04113; WO 95/19645
The disclosures in the following publications:
xe2x80x9cThree Dimensional Hybrid Wafer Scale Integration Using the GE High Density Interconnect Technologyxe2x80x9d by R. J. Wojnarowski, R. A Filliion, B. Gorowitz and R. Saia of General Electric Company, Corporate Research and Development, P.O. Box 8, Schenectady, N.Y. 12301, USA, International Conference on Wafer Scale Integration, 1993.
xe2x80x9cM-DENSUSxe2x80x9d, Dense-Pac Microsystems, Inc., Semiconductor International, December 1997, p. 50;
xe2x80x9cIntroduction to Cubic Memory, Inc.xe2x80x9d Cubic Memory Incorporated, 27 Janis Way, Scotts Valley, Calif. 95066, USA;
xe2x80x9cA Highly Integrated Memory Subsystem for the Smaller Wireless Devicesxe2x80x9d Intel(r) Stacked-CSP, Intel Corporation, January 2000;
xe2x80x9cProduct Construction Analysis (Stack CSP)xe2x80x9d, Sung-Fei Wang, ASE, R and D Group, Taiwan, 1999;
xe2x80x9cFour Semiconductor Manufacturers Agree to Unified Specifications for Stacked Chip Scale Packagesxe2x80x9d, Mitsubishi Semiconductors, Mitsubishi Electronics America, Inc., 1050 East Arques Avenue, Sunnyvale, Calif. 94086, USA;
xe2x80x9cAssembly and Packaging, John Baliga, Technology News, Semiconductor International, December 1999;
xe2x80x9c less than 6 mils Wafer Thickness Solution (DBG Technology)xe2x80x9d, Sung-Fei Wang, ASE, R and D Group, Taiwan, 1999;
xe2x80x9cMemory Modules Increase Densityxe2x80x9d, DensePac MicroSystems, Garden Grove, Calif., USA, Electronics Packaging and Production, p. 24, November 1994;
xe2x80x9cFirst Three-Chip Staked CSP Developedxe2x80x9d, Semiconductor International, January 2000, p. 22;
xe2x80x9cHigh-Density Packaging: The Next Interconnect Challengexe2x80x9d, Semiconductor International, February 2000, pp. 91-100;
xe2x80x9c3-D IC Packagingxe2x80x9d, Semiconductor International, p. 20, May 1998;
xe2x80x9cHigh Density Pixel Detector Module Using Flip Chip and Thin Film Technologyxe2x80x9d J. Wolf, P. Gerlach, E. Beyne, M. Topper, L. Dietrich, K. H. Becks, N. Wermes, O. Ehrmann and H. Reichl, International System Packaging Symposium, January 1999, San Diego;
xe2x80x9cCopper Wafer Bondingxe2x80x9d, A. Fan, A. Rahman and R. Rief, Electrochemical and Solid State Letters, 2(10), pp. 534-536, 1999;
xe2x80x9cFront-End 3-D Packagingxe2x80x9d, J. Baliga, Semiconductor International, December 1999, p 52,
are also believed to represent the state of the art.
The present invention seeks to provide improved packaged integrated circuits and methods for producing same.
There is thus provided in accordance with a preferred embodiment of the present invention a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.
Further in accordance with a preferred embodiment of the present invention the package is a chip-scale package.
Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is partially transparent to infra-red radiation.
There is also provided in accordance with another preferred embodiment of the present invention a packaged integrated circuit assembly including a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface and at least one additional electrical circuit element mounted onto and supported by the second planar surface and electrically coupled to at least one of the plurality of electrical contacts extending therealong.
Further in accordance with a preferred embodiment of the present invention the additional electrical circuit element includes an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
Still further in accordance with a preferred embodiment of the present invention the package is a chip-scale package.
There is further provided in accordance with a preferred embodiment of the present invention a method for producing packaged integrated circuits. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface and separating the integrated circuit substrate in the wafer scale packaging into a plurality of individual chip packages.
Further in accordance with a preferred embodiment of the present invention the plurality of individual chip packages are chip scale packages.
Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
There is also provided in accordance with yet another preferred embodiment of the present invention a method for producing packaged integrated circuit assemblies. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface, separating the integrated circuit substrate in the wafer scale packaging into a plurality of individual chip packages and mounting onto the at second planar surface of at least one of the plurality of individual chip packages, at least one additional electrical circuit element, the at least one additional electrical circuit element being supported by the second planar surface and electrically coupled to at least one of the plurality of electrical contacts extending therealong.
Further in accordance with a preferred embodiment of the present invention the additional electrical circuit element includes an electrical component selected from the group consisting of passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
There is further provided in accordance with yet another preferred embodiment of the present invention a method for producing packaged integrated circuit assemblies. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface, mounting onto the at second planar surface of the wafer scale packaging, at least one additional electrical circuit element, the at least one additional electrical circuit element being supported by the second planar surface and electrically coupled to at least one-of the plurality of electrical contacts extending therealong and separating the integrated circuit substrate in the wafer scale packaging into a plurality of individual chip packages.
Further in accordance with a preferred embodiment of the present invention the additional electrical circuit element includes an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.